VV6850 View Datasheet(PDF) - Vision

Part Name

Description

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VV6850

High resolution CMOS Image Sensor with support for external FPN cancellation and serial interface control, available in colour (6850) and monochrome (5850) versions

Vision 

VISION V V 6850 & 5850 Sensors: Product Datasheet Revision 1.0

The 5-Bit DAC

The internal five bit resistive ladder DAC is energised by a Bias Generator that is set by the inter-

nal Bandgap Voltage Reference, Vbg, and the external 12K resistor connected from Rset to

AGND. The Vdac output of the DAC, which can be used to set either VCL1 or VCL2, is adjusted

by bits 11 to 15 of the Control Register/Serial Interface.

AVCC

I = Vbg/122R

R ~ 100 Ohms

CR[15..11]

5-Bit DAC

Bias

Generator

32

Vbg

y Rset

r12K

aVdactop

i nVdac

l i m 176R

r eAGND

Vdac3/4

Vdacbot

P Note: The Vbg pin is a high impedance output, and can be over-ridden within the VCL input limits.

Parameter

Definition

Value

Comment

Vdactop

Vdacbot

Vdac3/4

Vdac

Zdac

208/122 * Vbg

2.08V

176/122 * Vbg

1.76V

199/122 * Vbg

1.99V

CR[15..11] * (32/122 * Vbg)

-

Vdac Output Impedance

21K

Ohms ±25%

5-Bit DAC Parameters

10

cd24011a.fm

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