MSK621 View Datasheet(PDF) - M.S. Kennedy
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MSK621 Datasheet PDF : 6 Pages
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APPLICATION NOTES
VIDEO INPUT
Pin 6 is the video input pin. The video input signal is coupled
to this point through a 30Ω, 10µF 'RC' filter as shown in figure
two. The MSK 621 is designed to receive input voltages as
high as ±13.5V.
OUTPUT
The distinguishing characteristic of the MSK 621 which sepa-
rates it from the MSK 620 is its output configuration. The
MSK 620 contains a push pull output capable of delivering ap-
proximately 25mA of load current. The MSK 621 has the same
output as the MSK 620 except it is followed by an emitter
follower buffer stage. This buffer stage increases the load cur-
rent capability to 100mA making the MSK 621 capable of driv-
ing a coax cable. The output buffer stage also allows the out-
put voltage to swing through zero volts.
POWER SUPPLY CONNECTIONS
Pin 13 is the positive power supply pin, and Pin 15 is the
negative power supply pin. Convenient internal power supply
decoupling consists of a parallel combination of three capaci-
tors ranging from 0.01µF to 0.47µF. The user is advised to
connect at least 4.7µF tantalum decoupling capacitors as close
to the power supply pins as possible.
Vref OUTPUT
Pin 9 is the Vref output pin. This pin connects to the output
of an ultra stable 5.0VDC reference voltage generator internal
to the MSK 621. This reference is used as a voltage source for
the contrast, drive and clamp inputs. (See figure one).
CONTRAST CONTROL
To achieve contrast control, pin 1 is shorted to pin 2 and pin
3 is shorted to pin 4. The voltages at pins 1 and 4 are con-
trolled by the input voltage at pin seven. As the voltage at pin
7 increases, the voltages at pins 1 and 4 become offset. With
pin 7 at zero volts and pin 8 at +4.0 volts, pins 1 an 4 are at
minimum offset and the contrast is set to the minimum value of
-38dB typical. With pin 7 at 4V, pins 1 and 4 are at maximum
offset and contrast is maximized to +26dB. Pin 7 is internaly
decoupled to ground with a 0.1uF capacitor.
DRIVE CONTROL
Pin 8 is the drive control input. This pin accepts a DC voltage
to control overall gain. Pin 8 is internally decoupled to ground
with a 0.1uF capacitor. With 0V at pin 8, the gain is minimum
(-6dB). With 4V at pin 8, the gain is maximum (0dB). Drive
control is approximated by the following formula:
CLAMP CONNECTIONS
Pin 16 is the (-) clamp input pin. This pin is the inverting
input to the clamp comparator. When the clamp comparator is
enabled, the voltage at pin 16 is compared to the voltage at pin
17, which is the non-inverting input of the clamp comparator.
A source or sink current is generated at pin 10 to charge or
discharge the clamp cap and supply DC bias to the video ampli-
fier. The DC voltage at pin 17 is user adjustable through a
100KΩ potentiometer voltage divider to Vref (see figure 2). In
DC coupled cathode drive applications, brightness can be var-
ied by varying the DC voltage at pin 17. Pin 16 is internally fed
back to the output prior to the buffer stage.
DC RESTORATION
Pin 11 is the clamp gate input pin and is driven by a TTL back
porch clamp signal. A voltage level of +1.3V or less is a "low
level" and a voltage level of +1.5V or greater is a "high level".
An active low level at this pin enables the clamp comparator
section so that DC restoration can be accomplished. This pin
should be held at a "high" logic level when a back porch clamp
signal is not used.
ATTENUATION (dB) = (1.5) x (DRIVE VOLTAGE) - (6dB)
See graph of Attenuation vs. Drive Control Voltage
CLAMP CAP
Pin 10 is the clamp comparator output pin. A capacitance of
approximately 0.1µF is connected from this pin to ground. Dur-
ing the "back porch" portion of the clamp signal, the clamp
capacitor is either charged or discharged to match the voltage
set on the non-inverting input of the clamp comparator (pin
16). During the video portion of the input signal, the clamp
comparator is disabled and the clamp cap holds the proper DC
bias in the video amplifier.
A typical single video channel connection diagram for the
MSK 621 is shown in figure one above. The DC voltage at pin
6 is internally fixed at +2.6V and the video signal is AC coupled
to the input. An internal reference voltage generator supplies a
+5.0VDC level at pin 9 for use with the contrast, drive and
brightness control potentiometers. With pin 7 at 0V, minimum
gain is realized. With pin 7 at 4V, maximum gain is realized.
The clamp gate input at pin 11 accepts a TTL level clamp signal
for DC restoration during the back porch segment of the video
signal. Pin 17 is the brightness control input pin and accepts a
zero to four volt DC level. This level sets the black level of the
signal. If pin 17=+1VDC the signal black level will be +1VDC.
3
Rev. A 8/00
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