VPC 3205C, VPC 3215C
PRELIMINARY DATA SHEET
Table 3–1: Control and status registers
I2C Sub- Number Mode
address of bits
h’35 8
r
h’36 16
w
h’37 16
w
h’38 16
w/r
h’12 16
w/r
h’1F 16
w/r
Function
Default Name
FP Interface
FP status
bit [0]
bit [1]
bit [2]
write request
read request
busy
bit[8:0]
bit[11:9]
9-bit FP read address
reserved, set to zero
bit[8:0]
bit[11:9]
9-bit FP write address
reserved, set to zero
bit[11:0]
FP data register, reading/writing to this
register will autoincrement the FP read/
write address. Only 16 bit of data are
transferred per I2C telegram.
Black Line Detector
read only register, do not write to this register! After reading,
LOWLIN and UPLIN are reset to 127 to start a new measure-
ment.
bit[6:0]
number of lower black lines
bit[7]
always 0
bit[14:8]
number of upper black lines
bit[15] 0/1
normal/black picture
Pin Circuits
SYNC pins (HS, HC, AVO, HELP, INTLC, VS):
bit[2:0] 0..7
output strength for SYNC Pins
(7 = tristate, 6 = weak ... 0 = strong)
bit[3] 0/1
pushpull/tristate for AVO Pin
bit[4] 0/1
pushpull/tristate for other SYNC Pins
bit[5] 0/1
synchronization/no synchronization with
horizontal HS for signals VS and INTLC
CLOCK pins (LLC1, LLC2):
bit[6] 0/1
pushpull/tristate for LLC1
bit[7] 0/1
pushpull/tristate for LLC2
DATA pins (LB[7:0], CB[7:0]):
bit[10:8] 0..7
output strength for DATA pins
(7 = tristate, 6 = weak ... 0 = strong)
bit[11] 0/1
tristate/pushpull for DATA pins
bit[12] 0/1
half-cycle pull-up(DIGIT3000)/pushpull for
LB, CB
(LCC)
bit[13]
reserved (set to 0)
bit[14:15]
output strength for LLC1: (–2,–1,0,1)
– FPSTA
– FPRD
– FPWR
– FPDAT
– BLKLIN
LOWLIN
UPLIN
BLKPIC
TRPAD
0 SNCSTR
0 AVODIS
0 SNCDIS
0 VASYSEL
0 LLC1DIS
0 LLC2DIS
0 DATSTR
0 DATEN
0 LCPUDIS
0 LLC1STR
18
Micronas