VPC3211C View Datasheet(PDF) - Micronas

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VPC3211C

VPC3205C, VPC3215C Video Processor Family

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PRELIMINARY DATA SHEET

VPC 3205C, VPC 3215C

2.4. Horizontal Scaler

The 4:2:2 YCrCb signal from the color decoder is pro-

cessed by the horizontal scaler. The scaler block

allows a linear or nonlinear horizontal scaling of the

input video signal in the range of 0.25 to 4. Nonlinear

scaling, also called “panorama vision”, provides a

geometrical distortion of the input picture. It is used to

fit a picture with 4:3 format on a 16:9 screen by stretch-

ing the picture geometry at the borders. Also, the

inverse effect can be produced by the scaler. A sum-

mary of scaler modes is given in Table 2–1.

The scaler contains a programmable decimation filter,

a 1-line FIFO memory, and a programmable interpola-

tion filter. The scaler input filter is also used for pixel

skew correction, see 2.3.9. The decimator/interpolator

structure allows optimal use of the FIFO memory. The

controlling of the scaler is done by the internal Fast

Processor.

Table 2–1: Scaler modes

Mode

Scale Description

Factor

Compression 0.75

4:3 → 16:9 linear

4:3 source displayed on

a 16:9 tube,

with side panels

Panorama

4:3 →16:9

non-

linear

compr

4:3 source displayed on

a 16:9 tube,

Borders distorted

Zoom

4:3 → 4:3

1.33

linear

Letterbox source (PAL+)

displayed on a 4:3 tube,

vertical overscan with

cropping of side panels

Panorama

4:3 → 4:3

non-

linear

zoom

Letterbox source (PAL+)

displayed on a 4:3 tube,

vertical overscan, bor-

ders distorted, no crop-

ping

20.25 →

13.5 MHz

0.66

sample rate conversion

to line-locked clock

2.5. Blackline Detector

In case of a letterbox format input video, e.g. Cinema-

scope, PAL+ etc., black areas at the upper and lower

part of the picture are visible. It is suitable to remove or

reduce these areas by a vertical zoom and/or shift

operation.

The VPC 32xx supports this feature by a letterbox

detector. The circuitry detects black video lines by

measuring the signal amplitude during active video.

For every field the number of black lines at the upper

and lower part of the picture are measured, compared

to the previous measurement and the minima are

stored in the I2C-register BLKLIN. To adjust the picture

amplitude, the external controller reads this register,

calculates the vertical scaling coefficient and transfers

the new settings, e.g. vertical sawtooth parameters,

horizontal scaling coefficient etc., to the VPC.

Letterbox signals containing logos on the left or right

side of the black areas are processed as black lines,

while subtitles, inserted in the black areas, are pro-

cessed as non-black lines. Therefore the subtitles are

visible on the screen. To suppress the subtitles, the

vertical zoom coefficient is calculated by selecting the

larger number of black lines only. Dark video scenes

with a low contrast level compared to the letterbox

area are indicated by the BLKPIC bit.

2.6. Control and Data Output Signals

The VPC 32xx supports two output modes: In

DIGIT3000 mode, the output interfaces run at the main

system clock, in line-locked mode, the VPC generates

an asynchronous line-locked clock that is used for the

output interfaces.

2.6.1. Line-Locked Clock Generation

An on-chip rate multiplier will be used to synthesize

any desired output clock frequency of 13.5/16/18 MHz.

A double clock frequency output is available to support

100 Hz systems. The synthesizer is controlled by the

embedded RISC controller, which also controls all

front-end loops (clamp, AGC, PLL1, etc.). This allows

the generation of a line-locked output clock regardless

of the system clock (20.25 MHz) which is used for

comb filter operation and color decoding. The control

of scaling and output clock frequency is kept indepen-

dent to allow aspect ratio conversion combined with

sample rate conversion. The line-locked clock circuity

generates control signals, e.g. horizontal/vertical sync,

active video output, it is also the interface from the

internal (20.25 MHz) clock to the external line-locked

clock system.

If no line-locked clock is required, i.e. in the DIGIT3000

mode, the system runs at the 20.25 MHz main clock.

The horizontal timing reference in this mode is pro-

vided by the front-sync signal. In this case, the

line-locked clock block and all interfaces run from the

20.25 MHz main clock. The synchronization signals

from the line-locked clock block are still available, but

for every line the internal counters are reset with the

main-sync signal. A double clock signal is not available

in DIGIT3000 mode.

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