CS51311GDR14 View Datasheet(PDF) - Cherry semiconductor

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CS51311GDR14

Synchronous CPU Buck Controller for 12V and 5V Applications

Cherry semiconductor 

Application Information: continued

When driving large capacitive loads, the COMP must

charge slowly enough to avoid tripping the CS51311 over-

current protection. The following equation can be used to

ensure unconditional startup:

ICHG

ILIM − ILOAD

<

CCOMP

COUT

where

ICHG = COMP Source Current (30µA typical);

CCOMP = COMP Capacitor value (0.1µF typical);

ILIM = Current Limit Threshold;

ILOAD = Load Current during startup;

COUT = Total Output Capacitance.

Normal Operation

During Normal operation, Switch Off-Time is constant and

set by the COFF capacitor. Switch On-Time is adjusted by

the V2TM Control loop to maintain regulation. This results in

changes in regulator switching frequency, duty cycle, and

output ripple in response to changes in load and line.

Output voltage ripple will be determined by inductor rip-

ple current and the ESR of the output capacitors

Slope Compensation

The V2TM control method uses a ramp signal, generated by

the ESR of the output capacitors, that is proportional to the

ripple current through the inductor. To maintain regulation,

the V2TM control loop monitors this ramp signal, through the

PWM comparator, and terminates the switch on-time.

The stringent load transient requirements of modern

microprocessors require the output capacitors to have very

low ESR. The resulting shallow slope presented to the

PWM comparator, due to the very low ESR, can lead to

pulse width jitter and variation caused by both random or

synchronous noise.

Adding slope compensation to the control loop, avoids

erratic operation of the PWM circuit, particularly at lower

duty cycles and higher frequencies, where there is not

enough ramp signal, and provides a more stable switch-

point.

The scheme that prevents that switching noise prematurely

triggers the PWM circuit consists of adding a positive volt-

age slope to the output of the Error Amplifier (COMP pin)

during an off-time cycle.

The circuit that implements this function is shown in

Figure 11.

Transient Response

The CS51311 V2TM Control Loop’s 200ns reaction time pro-

vides unprecedented transient response to changes in

input voltage or output current. Pulse-by-pulse adjustment

of duty cycle is provided to quickly ramp the inductor cur-

rent to the required level. Since the inductor current cannot

be changed instantaneously, regulation is maintained by

the output capacitor(s) during the time required to slew the

inductor current.

14

COMP

CS51311

11

GATE(L)

CCOMP

R2

C1 R1

To Synchronous FET

Overall load transient response is further improved

through a feature called “Adaptive Voltage Positioning”.

This technique pre-positions the output capacitors voltage

to reduce total output voltage excursions during changes

in load.

Holding tolerance to 1% allows the error amplifiers refer-

ence voltage to be targeted +25mV high without compro-

mising DC accuracy. A “Droop Resistor”, implemented

through a PC board trace, connects the Error Amps feed-

back pin (VFB) to the output capacitors and load and carries

the output current. With no load, there is no DC drop

across this resistor, producing an output voltage tracking

the Error amps, including the +25mV offset. When the full

load current is delivered, a 50mV drop is developed across

this resistor. This results in output voltage being offset -

25mV low.

Figure 11: Small RC filter provides the proper voltage ramp at the

beginning of each on-time cycle.

The ramp waveform is generated through a small RC filter

that provides the proper voltage ramp at the beginning of

each on-time cycle. The resistors R1 and R2 in the circuit of

Figure 11 form a voltage divider from the GATE(L) output,

superimposing a small artificial ramp on the output of the

error amplifier. It is important that the series combination

R1/R2 is high enough in resistance not to load down and

negatively affect the slew rate on the GATE(L) pin.

Protection and Monitoring Features

The result of Adaptive Voltage Positioning is that addition-

al margin is provided for a load transient before reaching

the output voltage specification limits. When load current

suddenly increases from its minimum level, the output

capacitor is pre-positioned +25mV. Conversely, when load

current suddenly decreases from its maximum level, the

output capacitor is pre-positioned -25mV. For best

Transient Response, a combination of a number of high fre-

quency and bulk output capacitors are usually used.

Over-Current Protection

A loss-less hiccup mode current limit protection feature is

provided, requiring only the COMP capacitor to imple-

ment. The CS51311 provides overcurrent protection by

sensing the current through a “Droop” resistor, using an

internal current sense comparator. The comparator com-

pares the voltage drop through the “Droop” resistor to an

internal reference voltage of 86mV (typical).

If the voltage drop across the “Droop” resistor exceeds this

threshold, the current sense comparator allows the fault

233

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