MX98728EC View Datasheet(PDF) - Macronix International

Part Name

Description

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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

EEPROM Interface Register: Reg1Ch, R/W, default=00h

Bit

1C.0

1C.1

1C.2

1C.3

1C.4

1C.5

1C.6

1C.7

Symbol

EECS*

EECK*

EEDI*

EEDO*

EESEL*

EELD*

HOLDREQ

HLDAACK

Description

Chip Select output to the external EEPROM clock device

Serial Clock output to the external EEPROM clock device, <1MHz.

Serial Data Input to the external EEPROM clock device

Serial Data Output from the external EEPROM clock device

Set to enable the external EEPROM write operation(write Select). Default 0 is

read.

Set to enable reloading the entire contents of the EEPROM just like the power-on

reset or the hardware reset. When the loading is done, this bit will be set by

GMAC automatically.

Reserved, default = 0.

Reserved, Read only.

Bus Integrity Check Timer: BICT (Reg1Dh), R/W, default=00h

Bit

1D.7-0

Symbol

BICT[7:0]*

Description

Bus Integrity Check Timer: Default is 00h, meaning no bus integrity check is

enabled. The time unit of this counter is 40ns. Value in this counter other than zero

will enable the bus integrity check. Any bus cycle longer than the timeout period

will cause the "termination of the current bus cycle", which can avoid the abnor-

mal bus hang and the bus dead lock. The BUSEI interrupt will be issued. LED0

and LED1 will both be flashing identically in 12.5Hz. The possible timeout period

ranges from 40ns to a maximum of 10.24us. This counter can be used to warn

long cycles so that the driver can tune the local DMA performance.

IO Data Port Page Pointer Register: IORDP (Reg.1Fh/1Eh), R/E, default=x000h

Bit

1E.7-0,

1F.3-0

Symbol

IORDP[11:0]

Description

IO Read Data Port Page Pointer [11:0] : Any read to IORD (Reg4C-4F) will be

mapped to the packet buffer address which consists of IORDP and the current

content of the internal byte counter (IORDPBC). IORDP can be pointed to any

page within the packet buffer space. IORDP[11:0] are mapped to MA[19:8]

during the data port access. IORDP can be increment automatically when

the current page is exhausted and if AUTOPUB is 0. This page pointer is usually

used by the driver to read multiple TX packets status in the packet memory. Bit

3A.1 ( STIORD/RRDYB ) is with IORDP and IORD if the SRDY pin is not

available on the system application.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

17

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