MX98728EC View Datasheet(PDF) - Macronix International

Part Name

Description

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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

3.6

BFS1*(MDO)

3.7

BFSTATUS*(MDI)

Normally used as BFS1 pin for test purpose, while in MII mode, it is

used as MII management write data (MDO) for MDIO pin's output data.

Normally used as BFSTATUS pin for test purpose, while in MII mode, it is

used as MII management read data (MDI) for MDIO pin's input data.

Last Transmitted Packet Status: LTPS ( Reg4h), RO, default=00h

Bit

Symbol

Description

4.0

CC0*

Collision Count Bit 0 :

4.1

CC1*

Collision Count Bit 1 :

4.2

CC2*

Collision Count Bit 2 :

4.3

CC3*

Collision Count Bit 3 : When CC[3:0] = 1111 and a new collision is detected, it is

called the excessive collision error which will abort the current packet. The TEI inter-

rupt bit will be set.

4.4

CRSLOST* Carrier Sense Lost : Set to indicate CRS was lost during the transmission. Default is

reset for the normal packet transmission.

4.5

UF*

TX FIFO Underflow : Set to indicate a underflow problem in the TX FIFO. An FIFOEI

interrupt is generated for the driver to resolve this problem.

4.6

OWC*

Out of Window Collision : Set to indicate a collision occurred after 64 bytes of data

has been transmitted. No retransmission will be issued.

4.7

TERR*

Transmit Error: Set to indicate the packet transmitted with error. Reset for the normal

packet transmission.

Last Received Packet Status: LRPS ( Reg5h), RO

Bit

Symbol

Description

5.0

BF*

RX Packet Buffer Full Error : 1 indicates the RX packet buffer is full.

5.1

CRC*

CRC error : The calculation is based on the integer multiple of bytes. Set to indicate the

CRC error for the received packet.

5.2

FAE*

Frame Alignment Error : Set to indicate an extra nibble is received which is not at the

octet boundary.This error is independent of the CRC detection.

5.3

FO*

FIFO Overrun : When set, an interrupt is generated. The driver must resolve this error.

5.4

RW*

Receive Watchdog : Set to indicate the frame length exceeds 2048 bytes. An interrupt

will be generated to the driver.

5.5

MF*

Multicast Frame address : Set to indicate the current frame has the multicast address.

5.6

RF*

Runt Frame : Set to indicate a frame length less than 64 or 60 bytes depending on

register 50.2 ( RUNTSIZE ), only meaningful when the Reg01h.3 PB bit is set. When

PB=1, a runt frame will be accepted & RI is set for receive interrupt. When PB=0, a runt

frame is rejected.

5.7

RERR*

Receive Error : Set to indicate a packet received with errors including CRC, FAE, FO,

RW error.

Notes : This LRPS register contains the same status byte as in the description field of the last received packet in

the packet memory.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

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