Overview
The QuickMIPS™ Embedded Standard Products (ESPs) family provides an out-of-the box solution consisting of the QL901M QuickMIPS chip and the QuickMIPS development environment. The development environment includes a Reference Design Kit (RDK) with drivers, real-time operating systems, and QuickMIPS system model. With the RDK, software and hardware engineers can evaluate, debug, and emulate their system in parallel.

CPU
• High-performance MIPS 4Kc processor runs up to 133 MHz in .25µ (173 Dhrystone MIPS)
• 1.3 Dhrystone MIPS per MHz
• MDU supports MAC instructions for DSP functions
• 16 Kbytes of Instruction Cache (4-way set associative)
• 16 Kbytes of Data Cache (4-way set associative) with lockout capability per line

High-Performance Bus (AMBA AHB)
• High-performance 32-bit AMBA AHB bus standard for high-speed system bus running at half the CPU clock
• High-bandwidth memory controller for SDRAM, SRAM, and EPROM
• SDRAM support for standard SDRAMs up to 256 MBytes with auto refresh, up to 4 banks non-interleaved
• Support for PC100 type memories with up to two chip enables
• EPROM controller for boot code
• 8-bit, 16-bit, and 32-bit device width support
• 16 Kbytes of on-chip, high-speed SRAM for use by multiple AHB Bus Masters
• 32-bit 66/33 MHz PCI Host and Satellite (Master/Target) operation with DMA channels and FIFO for full bandwidth
• Two MAC10/100s with MII ports connect easily to external transceivers/PHY devices
• One AHB 32-bit master port/one AHB 32-bit slave port to Programmable Fabric
• Global System Configuration and Interrupt Controller

Peripheral Bus (AMBA APB)
• 32-bit APB runs at half the CPU clock frequency (the same as the AHB clock)
• Three APB slave ports in the programmable fabric
• Two serial ports (one with Modem control signals and one with IRDA-compliant signals)
• Four general-purpose 32-bit timer/counters on one APB port

Programmable Via-Link Fabric
• Embedded memory configurable as RAM or FIFO
• 252 programmable I/Os
• High-speed dynamically configurable ECUs enable hardware implementation of DSP functions with 3-bit instructions
• Fabric I/O standard options: LVTLL, LVCMOS, PCI, GTL+, SSTL, and SSTL3

On-Chip Debug Blocks
• On-chip instrumentation blocks for debug and trace capabilities
• Configurable Logic Analysis Module (CLAM) blocks with IP in programmable fabric allow user to look at selected signals from IP function in fabric
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