
STMicroelectronics
Summary description
The NAND04GA3C2A and NAND04GW3C2A are a Multi-level Cell(MLC) devices from the NAND Flash 2112 Byte Page family of non-volatile Flash memories. The devices are offered in 1.8V and 3V VDDQ I/O power supplies. The core voltage is 3V VDD. The size of a Page is 2112 Bytes (2048 + 64 spare).
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 10,000 cycles. The devices also have hardware security features; a Write Protect pin is available to give hardware protection against Program and Erase operations.
FEATUREs
■ High density multi-level Cell (MLC) NAND Flash memories:
– Up to 128 Mbit spare area
– Cost effective solutions for mass storage applications
■ NAND interface
– x8 bus width
– Multiplexed Address/ Data
■ Supply voltages
– VDD = 2.7 to 3.6V core supply voltage for
Program, Erase and Read operations.
– VDDQ = 1.7 to 1.95 or 2.7 to 3.6V for I/O buffers.
■ Page size: (2048 + 64 spare) Bytes
■ Block size: (256K + 8K spare) Bytes
■ Page Read/Program
– Random access: 60µs (max)
– Sequential access: 60ns(min)
– Page Program Operation time: 800µs (typ)
■ Cache Read mode
– Internal Cache Register to improve the read throughput
■ Fast Block Erase
– Block erase time: 1.5ms (typ)
■ Status Register
■ Electronic Signature
■ Serial Number option
■ Chip Enable ‘don’t care’
– for simple interface with microcontroller
■ Data Protection
– Hardware Program/Erase locked during power transitions
■ Embedded Error Correction Code (ECC)
– Internal ECC accelerator
– Easy ECC Command Interface
■ Data integrity
– 10,000 Program/Erase cycles (with ECC)
– 10 years Data Retention
■ ECOPACK® package available
■ Development tools
– Bad Blocks Management and Wear Leveling algorithms
– File System OS Native reference software
– Hardware simulation models