
STMicroelectronics
SUMMARY DESCRIPTION
The NAND Flash 2112 Byte/ 1056 Word Page is a family of non-volatile Flash memories that uses NAND cell technology. The devices range from 512 Mbits to 8 Gbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 2112 Bytes (2048 + 64 spare) or 1056 Words (1024 + 32 spare) depending on whether the device has a x8 or x16 bus width.
FEATURES SUMMARY
◾ HIGH DENSITY NAND FLASH MEMORIES
– Up to 8 Gbit memory array
– Up to 64Mbit spare area
– Cost effective solutions for mass storage
applications
◾ NAND INTERFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
◾ SUPPLY VOLTAGE
– 1.8V device: VDD = 1.7 to 1.95V
– 3.0V device: VDD = 2.7 to 3.6V
◾ PAGE SIZE
– x8 device: (2048 + 64 spare) Bytes
– x16 device: (1024 + 32 spare) Words
◾ BLOCK SIZE
– x8 device: (128K + 4K spare) Bytes
– x16 device: (64K + 2K spare) Words
◾ PAGE READ / PROGRAM
– Random access: 25µs (max)
– Sequential access: 50ns (min)
– Page program time: 300µs (typ)
◾ COPY BACK PROGRAM MODE
– Fast page copy without external buffering
◾ CACHE PROGRAM AND CACHE READ
MODES
– Internal Cache Register to improve the
program and read throughputs
◾ FAST BLOCK ERASE
– Block erase time: 2ms (typ)
◾ STATUS REGISTER
◾ ELECTRONIC SIGNATURE
◾ CHIP ENABLE ‘DON’T CARE’
– for simple interface with microcontroller
◾ AUTOMATIC PAGE 0 READ AT POWER-UP
– Boot from NAND support
◾ SERIAL NUMBER OPTION
Figure 1. Packages
◾ DATA PROTECTION
– Hardware and Software Block Locking
– Hardware Program/Erase locked during
Power transitions
◾ DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
◾ RoHS COMPLIANCE
– Lead-Free Components are Compliant
with the RoHS Directive
◾ DEVELOPMENT TOOLS
– Error Correction Code software and
hardware models
– Bad Blocks Management and Wear
Leveling algorithms
– PC Demo board with simulation software
– File System OS Native reference software
– Hardware simulation models