256 MBit Synchronous DRAM

The HYB 39S256400/800/160T are four bank Synchronous DRAM’s organized as 4 banks × 16 MBit ×4, 4 banks × 8 MBit ×8 and 4 banks × 4 MBit ×16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology.

Preliminary  Information
• High Performance:
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3, 4
• Programmable Wrap Sequence: Sequential  or Interleave
• Programmable Burst Length:  1, 2, 4, 8
• Multiple Burst Read with Single Write  Operation
• Automatic and Controlled Precharge  Command
• Data Mask for Read/Write control (×4, ×8)
• Data Mask for byte control (×16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 8192 refresh cycles/64 ms 7,8 µ
• Random Column Address every CLK  (1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages: P-TSOPII-54 400mil width (×4, ×8, ×16)
• -8 part for PC100 2-2-2 operation
  -8B part for PC100 3-2-3 operation
  -10 part for PC66 2-2-2 operation