Operating Range:
• Up to 40 MIPS operation (@ 3.0-3.6V):
   - Industrial temperature range (-40°C to +85°C)
   - Extended temperature range (-40°C to +125°C)
• Up to 20 MIPS operation (@ 3.0-3.6V):
   - High temperature range (-40°C to +150°C)

High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide dat path
• 24-bit wide instructions
• Linear program memory addressing up to 4M instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
• Sixteen 16-bit General Purpose Registers
• Two 40-bit accumulators:
   - With rounding and saturation options
• Flexible and powerful addressing modes:
   - Indirect, Modulo and Bit-Reversed
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate:
   - Accumulator write back for DSP operations
   - Dual data fetch
• Up to ±16-bit shifts for up to 40-bit data

Direct Memory Access (DMA):
• 8-channel hardware DMA:
• 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
• Most peripherals support DMA

Interrupt Controller:
• 5-cycle latency
• Up to 63 available interrupt sources
• Up to five external interrupts
• Seven programmable priority levels
• Five processor exceptions

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