Features
• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
• 250-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
   (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
   — SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
   and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in
   high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• 15 x 17 x 1.4 mm 1.0-mm pitch fBGA package,
   165 ball (11x15 matrix)
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement