CP588V 数据手册 ( 数据表 ) - Central Semiconductor
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Central Semiconductor
PROCESS DETAILS
Process EPITAXIAL PLANAR
Die Size 14.6 x 14.6 MILS
Die Thickness 7.1 MILS
Base Bonding Pad Area 3.9 x 3.9 MILS
Emitter Bonding Pad Area 5.5 x 5.5 MILS
Top Side Metalization Al - 30,000Å
Back Side Metalization Au - 18,000Å
Small Signal Transistor PNP - Low Noise Amplifier Transistor Chip
Central Semiconductor
Small Signal Transistor PNP - Low Noise Amplifier Transistor Chip ( Rev : 2002 )
Central Semiconductor
Small Signal Transistor PNP - Low Noise Amplifier Transistor Chip
Central Semiconductor
Small Signal Transistor NPN - Low Noise Amplifier Transistor Chip
Central Semiconductor
Small Signal Transistor NPN - Low Noise Amplifier Transistor Chip
Central Semiconductor
Small Signal Transistor NPN - Low Noise Amplifier Transistor Chip ( Rev : 2002 )
Central Semiconductor
Small Signal Transistor PNP - Low VCE(SAT) Transistor Chip
Central Semiconductor
Small Signal Transistor PNP - Darlington Transistor Chip ( Rev : 2002 )
Central Semiconductor
Small Signal Transistor PNP - Darlington Transistor Chip
Central Semiconductor
PNP, LOW NOISE AMPLIFIER TRANSISTOR
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