Description 
   The AT52BR3224A(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM (organized as 256K x 16) in a stacked 66-ball CBGA package. The AT52BR3228A(T) combines a 32-megabit Flash (2M x 16) and an 8-megabit SRAM (organized as 512K x 16) in a stacked 66-ball CBGA package. The stacked modules operate at 2.7V to 3.3V in the industrial temperature range.

FEATUREs
• 32-Mbit Flash and 4-Mbit/8-Mbit SRAM
• Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
• 2.7V to 3.3V Operating Voltage

Flash
• 2.7V to 3.3V Read/Write
• Access Time – 70 ns
• Sector Erase Architecture
   – Sixty-three 32K WordSectors with Individual Write Lockout
   – Eight 4K Word Sectors with Individual Write Lockout
• Fast Word Program Time – 15 µs
• Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
   – Supports Reading and Programming from Any Sector by Suspending Erase of a
      Different Sector
   – Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
   – 12 mA Active
   – 13 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program/Erase Operations
• RESET Input for Device Initialization
• Sector Lockdown Support
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles

SRAM
• 4-megabit (256K x 16)/8-megabit (512K x 16)
• 2.7V to 3.3V VCC
• 70 ns Access Time
• Fully Static Operation and Tri-state Output
• 1.2V (Min) Data Retention
• Industrial Temperature Range