5V/3.3V 32K×16 CMOS SRAM

The AS7C513 and the AS7C3513 are high performance CMOS 524,288-bit Static Random Access Memory (SRAM) devices organized as 32,768 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 5/7/9 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.

• AS7C513 (5V version)
• AS7C3513 (3.3V version)
• Industrial and commercial temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins
• High speed
   - 12/15/20 ns address access time
   - 5/7/9 ns output enable access time
• Low power consumption: ACTIVE
   - 800 mW (AS7C513) / max @ 12 ns
   - 432 mW (AS7C3513) / max @ 12 ns
• Low power consumption: STANDBY
   - 28 mW (AS7C513) / max CMOS
   - 18 mW (AS7C3513) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
   - 400 mil SOJ
   - 400 mil TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA