GENERAL DESCRIPTION
   The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134, 217, 728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33, 554, 432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.

FEATURES
• Full Military temp (-55°C to 125°C) processing available
• Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Fully synchronous; all signals registered on positive
   edge of system clock
• Internal pipelined operation; column address can be
   changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
   PRECHARGE and Auto Refresh Modes
• Self Refresh Mode (IT)
• 64ms, 4,096-cycle refresh (IT)
• <24ms 4,096 cycle recfresh (XT)
• WRITE Recovery (tWR = “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply