GENERAL DESCRIPTION
The ADSP-21266 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Harvard Architecture. The ADSP-21266 is source code compatible with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. Like other SHARC DSPs, the ADSP-21266 is a 32-bit/40-bit floating-point processor optimized for high performance audio applications with its dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface.

SUMMARY
    High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing
    Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs
    The ADSP-21266 processes high performance audio while enabling low system costs
    Audio decoders and post processor algorithms support: Nonvolatile memory can be configured to contain a combination of PCM 96 kHz, Dolby® Digital, Dolby Digital Surround EXTM, DTS-ESTM Discrete 6.1, DTS-ES Matrix 6.1, DTS® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMAPRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6TM
    Various multichannel surround-sound decoders are contained in ROM. For configurations of decoder algorithms, see Table 2 on Page 6.
    Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file
    High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital audio interface (DAI), and JTAG
    DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)
    On-chip memory—2M bits of on-chip SRAM and a dedicated 4M bits of on-chip mask-programmable ROM
    The ADSP-21266 is available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page 44.