零件编号
AD9512UCPZ-EP
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AD9512UCPZ-EP 数据手册 ( 数据表 ) - Analog Devices
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GENERAL DESCRIPTION
The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part.
There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.
FEATURES
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
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1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs ( Rev : RevA )
Analog Devices
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs ( Rev : Rev0 )
Analog Devices
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
Analog Devices
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs ( Rev : RevB )
Analog Devices
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs ( Rev : RevC )
Analog Devices
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs ( Rev : RevC )
Analog Devices
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