Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

FEATUREs
• Single 3.3V(±10 %) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active mode : 432/396 mW (Mas)
   - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)