General description

   The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW.

Features and benefits

◾ Automotive product qualification in accordance with AEC-Q100 (Grade 1)

   ✦ Specified from -40 °C to +85 °C and from -40 °C to +125 °C

◾ Input levels:

   ✦ For 74HC175-Q100: CMOS level

   ✦ For 74HCT175-Q100: TTL level

◾ Four edge-triggered D-type flip-flops

◾ Asynchronous master reset

◾ Complies with JEDEC standard no. 7A

◾ ESD protection:

   ✦ MIL-STD-883, method 3015 exceeds 2000 V

   ✦ HBM JESD22-A114F exceeds 2000 V

   ✦ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

◾ Multiple package options