General description
The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

FEATUREs and benefits
■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    ◆ Specified from -40 °C to +85 °C and from -40 °C to +125 °C
■ Input levels:
    ◆ For 74HC74-Q100: CMOS level
    ◆ For 74HCT74-Q100: TTL level
■ Symmetrical output impedance
■ Low power dissipation
■ High noise immunity
■ Balanced propagation delays
■ Specified in compliance with JEDEC standard no. 7A
■ ESD protection:
    ◆ MIL-STD-883, method 3015 exceeds 2000 V
    ◆ HBM JESD22-A114F exceeds 2000 V
    ◆ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
■ Multiple package options