General description
The 74HC4040-Q100; 74HCT4040-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

FEATUREs and benefits
■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    ◆ Specified from -40 °C to +85 °C and from -40 °C to +125 °C
■ Complies with JEDEC standard no. 7A
■ Input levels:
    ◆ For 74HC4040-Q100: CMOS level
    ◆ For 74HCT4040-Q100: TTL level
■ ESD protection:
    ◆ MIL-STD-883, method 3015 exceeds 2000 V
    ◆ HBM JESD22-A114F exceeds 2000 V
    ◆ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
■ Multiple package options

APPLICATIONs
■ Frequency dividing circuits
■ Time delay circuits
■ Control counters