
Intel
Introduction
The Dual-Core Intel® Xeon® Processor 5000 series are Intel dual core products for dual processor (DP) servers and workstations. The Dual-Core Intel Xeon Processor 5000 series are 64-bit server/workstation processors utilizing two physical Intel NetBurst® microarchitecture cores in one package. The Dual-Core Intel Xeon Processor 5000 series include enhancements to the Intel NetBurst microarchitecture while maintaining the tradition of compatibility with IA-32 software. Some key features include Hyper Pipelined Technology and an Execution Trace Cache. Hyper Pipelined Technology includes a multi-stage pipeline depth, allowing the processor to reach higher core frequencies. The Dual-Core Intel Xeon Processor 5000 series contain a total of 4 MB of L2 Advanced Transfer Cache, 2 MB per core. The 1066 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making 8.5 GBytes per second data transfer rates possible. The 667 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 166 MHz system clock making 5.3 GBytes per second data transfer rates possible.
FEATUREs
■ Dual-Core processor
■ Available at 3.73 GHz processor speed
■ Includes 16-KB Level 1 data cache per core (2 x 16-KB)
■ Includes 12-KB Level 1 trace cache per core (2 x 12-KB)
■ 2-MB Advanced Transfer Cache per core (2 x 2-MB, On-die, full speed Level 2 (L2) Cache) with 8- way associativity and Error Correcting Code (ECC)
■ 667/1066 MHz front side bus
■ 65 nm process technology
■ Dual processing (DP) server support
■ Intel® NetBurst® microarchitecture
■ Hyper-Threading Technology allowing up to 8 threads per platform
■ Hardware support for multi-threaded applications
■ Intel® Virtualization Technology
■ Intel® Extended Memory 64 Technology (Intel® EM64T)
■ Execute Disable Bit (XD Bit)
■ Enables system support of up to 64 GB of physical memory
■ Enhanced branch prediction
■ Enhanced floating-point and multimedia unit for enhanced video, audio, encryption, and 3D performance
■ Advanced Dynamic Execution
■ Very deep out-of-order execution
■ System Management mode
■ Machine Check Architecture (MCA)
■ Interfaces to Memory Controller Hub