STA014 查看數據表（PDF） - STMicroelectronics
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STA014
STMicroelectronics
STA014 Datasheet PDF : 45 Pages
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STA014-STA014B-STA014T
The following 4 figures (fig. 12, 13, 14, 15) show
the available connection diagrams as far as
ADPCM encoding function. As shown in the fig-
ures some configuration is not available in SO28
package.
Figure 12. Input from BITSTREAM, Output from
I2C
MCU
SDI
SCKR
DATA_REQ
BIT_EN
I2C
SO28
TQFP44
LFBGA64
LRCKT
SCKT
SDO
OCLK
DAC
D99AU1121A
STA013 compatible mode
Figure 14. Input from BITSTREAM, Output from
GPSO
GPSO_DATA
GPSO_SCKR
GPSO_REQ
SDI
SCKR
MCU
DATA_REQ
BIT_EN
I2C
TQFP44
LFBGA64
5 - I2C BUS SPECIFICATION
LRCKT
SCKT
SDO
OCLK
DAC
D99AU1122A
The STA014 supports the I2C protocol. This pro-
tocol defines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master always starts the
transfer and provides the serial clock for synchro-
nisation. The STA014 is always a slave device in
all its communications.
Figure 13. Input from ADC, Output from I2C +
IRQ
I2C
DATA_REQ
LRCKT
SCKT
MCU
ADC
SLAVE
SDI_ADC
SO28
TQFP44
LFBGA64
SDO
OCLK
DAC
MCU
ADC
MASTER
I2C
DATA_REQ
LRCK_ADC
SCK_ADC
SDI_ADC
SO28
TQFP44
LFBGA64
LRCKT
SCKT
SDO
OCLK
DAC
D99AU1123A
Figure 15. Input from ADC, Output from GPSO
MCU
GPSO_DATA
GPSO_SCKR
GPSO_REQ
ADC
MASTER
LRCK_ADC
SCK_ADC
SDI_ADC
TQFP44
LFBGA64
LRCKT
SCKT
SDO
OCLK
DAC
D99AU1124A
5. 1 - COMMUNICATION PROTOCOL
5.1.0 - Data transition or change
Data changes on the SDA line must only occur
when the SCL clock is low. SDA transition while
the clock is high are used to identify START or
STOP condition.
5.1.1 - Start condition
START is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state.
A START condition must precede any command
for data transfer.
12/45
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