DS3514TR 查看數據表（PDF） - Maxim Integrated

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DS3514TR

I2C Gamma and VCOM Buffer with EEPROM

Maxim Integrated 

I2C Gamma and VCOM Buffer with EEPROM

Control Register 48h: Control Register (CR)

FACTORY DEFAULT

20h

MEMORY TYPE

NV

48h

x

x

BIAS1

BIAS0

x

BIT 7

x

MODE1

MODE0

BIT 0

Bits 7:6

Bits 5:4

Bits 3:2

Bits 1:0

Reserved

VCOM and Gamma Bias Current Control Bits (BIAS[1:0]):

00 = 60%

01 = 80%

10 = 100% (default)

11 = 150%

Reserved

DS3514 Mode (MODE[1:0]):

00 = S0/S1 pins are used to select the desired bank (A–D) (default).

01 = SOFT S0/S1 (bits) are used to select the desired bank (A–D).

1X = Latch A is used to control the DACs.

Status Bits Register 4Ah: Real-Time Indicator of Logic State on LD, S1, and S0 Pins

FACTORY DEFAULT

—

MEMORY TYPE

Read Only

4Ah

LD

x

x

x

x

x

BIT 7

S1

S0

BIT 0

GDATx Register: EEPROM Data for the Gamma Channels

This is an example of how the bits are arranged for a typical GDATx memory location. GDATx has 10 bits that are

arranged in two consecutive bytes. The following example shows the arrangement for GM1 GDAT1 (58h–59h). This

arrangement is applicable for all the EEPROM data for all gamma channels.

FACTORY DEFAULT

MEMORY TYPE

8000h

NV

58h GDAT[9]

59h GDAT[1]

BIT 7

GDAT[8]

GDAT[0]

GDAT[7]

x

GDAT[6]

x

GDAT[5]

x

GDAT[4]

x

GDAT[3]

x

GDAT[2]

x

BIT 0

16 ______________________________________________________________________________________

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