ART2815T/CK(2006) 查看數據表（PDF） - International Rectifier
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ART2815T/CK
(Rev.:2006)
(Rev.:2006)
International Rectifier
ART2815T/CK Datasheet PDF : 12 Pages
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ART28XXT Series
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Group A
MIN
MAX
Test
Symbol Conditions unless otherwise specified Subgroups
Output voltage accuracy
Output power Note 1
Output current
Note 1
Output regulation Note 4
Input current
Output ripple Note 2
Input ripple Note 2
Switching frequency
Efficiency
VOUT
POUT
IOUT
VR
IIN
VRIP
IRIP
FS
Eff
IOUT = 1.5 Adc
(main)
IOUT = ±250mAdc
IOUT = ±250mAdc
VIN = 19 V, 28V, 50 V
VIN 19 V, 28V, 50 V
ART2812(dual)
ART2815(dual)
(main)
(dual)
IOUT = 150, 1500, 3000mAdc
VIN = 19 V, 28V, 50 V
IOUT = ±75, ±310, ±625mAdc
IOUT = ±75, ±250, ±500mAdc
(main)
2812(dual)
2815(dual)
IOUT = minimum rated, Pin 3 open
Pin 3 shorted to pin 2 (disabled)
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
Synchronization pin (pin 6) open
IOUT = 3000mA main, ±500mA dual
Power dissipation,
load fault
Output response to step
load changes Notes 3, 5
Recovery time from step
load changes Notes 5, 6
Turn on overshoot
Turn on delay Note 7
Isolation
PD Short circuit, any output
10% Load to/from 50% load
VTL
50% Load to/from 100% load
10% Load to/from 50% load
TTL
50% Load to/from 100% load
VOS IOUT = minimum and full rated
(main)
(dual)
TDLY IOUT = minimum and full rated
ISO 500VDC Input to output or any pin to case
(except pin 12)
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
4, 5, 6
1
2, 3
1, 2, 3
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
1
4.95
±11.70
±14.50
3.0
150
75
4.8
±11.1
±14.0
5.05
±12.30
±15.15
30
3000
500
5.2
±12.9
±15.8
250
8.0
70
100
225
275
83
81
16
-200
200
-200
200
200
200
100
500
5.0
20
100
Notes to Group A Test Table
1. Parameter verified during dynamic load regulation tests.
2. Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
3. Load current is stepped for output under test while other outputs are fixed at half rated load.
4. Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
5. Load step transition time ≥ 10µS.
6. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
7. Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
8. Subgroups 1 and 4 are performed at +25ºC, subgroups 2 and 5 at -55ºC and subgroups 3 and 6 at +125ºC.
Units
V
W
mA
V
mA
mVP-P
mAP-P
KHz
%
W
mVPK
µSs
mV
mSs
MΩ
4
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