MB39C022JPN 查看數據表（PDF） - Cypress Semiconductor

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MB39C022JPN

Buck DC/DC Converter + Low Noise LDO

Cypress Semiconductor 

Example 3 (POR and RC Delay Channel Control)

• EN1 is controlled by RC delay and EN2 is controlled by POR output.

• It is possible to control each channel without signal from MCU

MB39C022G/J/L/N

VO2

IO2 ≤ 300 mA

POR

R3

C4

C5

(MB39C022)

EN2

GND1

VIN2

LX

VOUT2

VIN1

POR

EN1

GND2

FB

C2

L1

C1

R5

R6

VO1

IO1 ≤ 600 mA

VIN

100 kΩ

1 μF

C3

Timing chart

VIN

VO1

(1.2 V)

VO2

(1.8 V)

tc

ta

tb

td

Start up control

ta : RC delay time (28 ms at VIN = 3.7 V, R = 100 kΩ, C = 1 μF)

tb : POR hold time (66 ms fixed)

Power down control

tc, td : depend on internal discharge path and output loading

VUVLO

Vth(POR)

Document Number: 002-08460 Rev. *C

Page 25 of 29

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