CLRC632 查看數據表（PDF） - NXP Semiconductors.

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CLRC632

Standard multi-protocol reader solution

NXP Semiconductors. 

NXP Semiconductors

23. Figures

Fig 1. CLRC632 block diagram . . . . . . . . . . . . . . . . . . . .4

Fig 2. CLRC632 pin configuration . . . . . . . . . . . . . . . . . .5

Fig 3. Connection to microprocessor: separate read

and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .8

Fig 4. Connection to microprocessor: common read

and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 5. Connection to microprocessor: EPP common

read/write strobes and handshake. . . . . . . . . . . . .9

Fig 6. Connection to microprocessor: SPI . . . . . . . . . . .10

Fig 7. Key storage format . . . . . . . . . . . . . . . . . . . . . . .18

Fig 8. Timer module block diagram . . . . . . . . . . . . . . . .24

Fig 9. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 10. The StartUp procedure. . . . . . . . . . . . . . . . . . . . .29

Fig 11. Quartz clock connection . . . . . . . . . . . . . . . . . . .30

Fig 12. Receiver circuit block diagram . . . . . . . . . . . . . . .35

Fig 13. Automatic Q-clock calibration . . . . . . . . . . . . . . .36

Fig 14. Serial signal switch block diagram . . . . . . . . . . . .38

Fig 15. Crypto1 key handling block diagram . . . . . . . . . .42

Fig 16. Transmitting bit oriented frames . . . . . . . . . . . . .80

Fig 17. Timing for transmitting byte oriented frames . . . .81

Fig 18. Timing for transmitting bit oriented frames. . . . . .81

Fig 19. Card communication state diagram . . . . . . . . . . .86

Fig 20. Timing for transmitting byte oriented frames . . . .88

Fig 21. Label communication state diagram . . . . . . . . . .92

Fig 22. EEPROM programming timing diagram. . . . . . . .94

Fig 23. Separate read/write strobe timing diagram . . . .103

Fig 24. Common read/write strobe timing diagram . . . .104

Fig 25. Timing diagram for common read/write strobe;

EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Fig 26. Timing diagram for SPI . . . . . . . . . . . . . . . . . . .106

Fig 27. Application example circuit diagram: directly

matched antenna . . . . . . . . . . . . . . . . . . . . . . . .107

Fig 28. TX control signals . . . . . . . . . . . . . . . . . . . . . . . 111

Fig 29. RX control signals . . . . . . . . . . . . . . . . . . . . . . . 112

Fig 30. ISO/IEC 14443 A receiving path Q-clock. . . . . . 114

Fig 31. I-CODE1 receiving path Q-clock . . . . . . . . . . . . 115

Fig 32. Package outline SOT287-1 . . . . . . . . . . . . . . . . 116

CLRC632

Standard multi-protocol reader solution

CLRC632

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.7 — 27 February 2014

073937

© NXP Semiconductors N.V. 2014. All rights reserved.

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