LTC6992HS6-1-WTRMPBF 查看數據表（PDF） - Analog Devices

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LTC6992HS6-1-WTRMPBF

TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)

Analog Devices 

LTC6992-1/LTC6992-2/

LTC6992-3/LTC6992-4

OPERATION

Changing DIVCODE After Start-Up

Following start-up, the A/D converter will continue moni-

toring VDIV for changes. Changes to DIVCODE will be

recognized slowly, as the LTC6992 places a priority on

eliminating any “wandering” in the DIVCODE. The typi-

cal delay depends on the difference between the old and

new DIVCODE settings and is proportional to the master

oscillator period.

tDIVCODE = 16 • (∆DIVCODE + 6) • tMASTER

A change in DIVCODE will not be recognized until it is

stable, and will not pass through intermediate codes.

A digital filter is used to guarantee the DIVCODE has set-

tled to a new value before making changes to the output.

Then the output will make a clean (glitchless) transition

to the new divider setting.

DIV

0.5V/DIV

512µs

Start-Up Time

When power is first applied, the power-on reset (POR)

circuit will initiate the start-up time, tSTART. The OUT pin

is held low during this time. The typical value for tSTART

ranges from 0.5ms to 8ms depending on the master oscil-

lator frequency (independent of NDIV):

tSTART(TYP) = 500 • tMASTER

The output will begin oscillating after tSTART. If POL = 0

the first pulse has the correct width. If POL = 1 (DIVCODE

≥ 8), the first pulse width can be shorter or longer than

expected, depending on the duty cycle setting, and will

never be less than 25% of tOUT.

During start-up, the DIV pin A/D converter must determine

the correct DIVCODE before the output is enabled. The

start-up time may increase if the supply or DIV pin volt-

ages are not stable. For this reason, it is recommended to

minimize the capacitance on the DIV pin so it will properly

track V+. Less than 100pF will not affect performance.

OUT

1V/DIV

V+ = 3.3V

RSET = 200k

VMOD = 0.3V

100µs/DIV

6992 F05

Figure 5. DIVCODE Change from 3 to 1

V+

DIV

STABLE VDIV

tDIVCODE

tSTART

OUT

1ST PULSE WIDTH MAY BE INACCURATE

6992 F06

Figure 6. Start-Up Timing Diagram

For more information www.analog.com

Rev. D

19

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