AS7C3513(2000) 查看數據表（PDF） - Alliance Semiconductor
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AS7C3513 Datasheet PDF : 8 Pages
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Parameter
VCC for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
Symbol
VDR
ICCDR
tCDR
tR
| ILI |
Test conditions
Min
Max
Unit
2.0
VCC = 2.0V
–
CE ≥ VCC–0.2V
0
VIN ≥ VCC–0.2V or
VIN ≤ 0.2V
tRC
–
–
V
500
µA
–
ns
–
ns
1
µA
Data retention mode
VCC
VCC
VDR ≥ 2.0V
VCC
tCDR
tR
CE
VIH
VDR
VIH
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Ω
Ω
Ω
Ω
Ω
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to the commercial operating range only.
14 C=30pF, except on High Z and Low Z parameters, where C=5pF.
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