LTC1296B 查看數據表（PDF） - Linear Technology
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LTC1296B Datasheet PDF : 28 Pages
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LTC1293/LTC1294/LTC1296
APPLICATI S I FOR ATIO
8051 CODE
LABEL MNEMONIC
SETB
CONT MOV
CLR
MOV
LOOP1 RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
LOOP MOV
RLC
SETB
CLR
DJNZ
MOV
MOV
SETB
OPERAND
P1.4
A,#87H
P1.4
R4,#08H
A
P1.3
P1.2,C
P1.3
R4,LOOP1
P1,#04H
P1.3
R4,#09H
C,P1.2
A
P1.3
P1.3
R4,LOOP
R2,A
C,P1.2
P1.3
COMMENTS
CS GOES HIGH
DIN WORD FOR LTC1294
CS GOES LOW
LOAD COUNTER
ROTATE DIN BIT INTO CARRY
CLK GOES LOW
OUTPUT DIN BIT TO LTC1294
CLK GOES HIGH
NEXT DIN BIT
P1.2 BECOMES AN INPUT
CLK GOES LOW
LOAD COUNTER
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B3) INTO ACC
CLK GOES HIGH
CLK GOES LOW
NEXT DOUT BIT
STORE MSBs IN R2
READ DATA BIT INTO CARRY
CLK GOES HIGH
LABEL MNEMONIC
CLR
CLR
RLC
MOV
RLC
SETB
CLR
MOV
RLC
SETB
CLR
MOV
SETB
RRC
RRC
RRC
RRC
MOV
AJMP
OPERAND
P1.3
A
A
C,P1.2
A
P1.3
P1.3
C,P1.2
A
P1.3
P1.3
C,P1.2
P1.4
A
A
A
A
R3,A
CONT
COMMENTS
CLK GOES LOW
CLEAR ACC
ROTATE DATA BIT (B3) INTO ACC
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B2) INTO ACC
CLK GOES HIGH
CLK GOES LOW
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B1) INTO ACC
CLK GOES HIGH
CLK GOES LOW
READ DATA BIT INTO CARRY
CS GOES HIGH
ROTATE DATA BIT (B0) INTO ACC
ROTATE RIGHT INTO ACC
ROTATE RIGHT INTO ACC
ROTATE RIGHT INTO ACC
STORE LSBs IN R3
START NEXT CONVERSION
21 0
OUTPUT PORT
3
SERIAL DATA
3
MPU
CS
LTC1294
3
CS
LTC1294
3
CS
LTC1294
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1293/4/6s
8 CHANNELS 8 CHANNELS 8 CHANNELS
Figure 3. Several LTC1294 Sharing One 3-Wire Serial Interface
LTC1293 F03
Sharing the Serial Interface
The LTC1293/4/6 can share the same 3-wire serial inter-
face with other peripheral components or other LTC1293/
4/6’s (Figure 3). Now, the CS signals decide which LTC1293/
4/6 is being addressed by the MPU.
ANALOG CONSIDERATIONS
Grounding
The LTC1293/4/6 should be used with an analog ground
plane and single point grounding techniques. Do not use
wire wrapping techniques to breadboard and evaluate the
device. To achieve the optimum performance use a PC
board. The analog ground pin (AGND) should be tied
directly to the ground plane with minimum lead length (a
low profile socket is fine). The digital ground pin (DGND)
also can be tied directly to this ground pin because
minimal digital noise is generated within the chip itself.
VCC should be bypassed to the ground plane with a 22µF
(minimum value) tantalum with leads as short as possible
and as close as possible to the pin. A 0.1µF ceramic disk
also should be placed in parallel with the 22µF and again
with leads as short as possible and as close to VCC as
possible. AVCC and DVCC should be tied together on the
17
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