CY8C5265AXI-LP056 查看數據表（PDF） - Cypress Semiconductor

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CY8C5265AXI-LP056

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 5LP: CY8C52LP Family

Datasheet

5.5 Nonvolatile Latches (NVLs)

PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown

in Table 5-3.

Table 5-2. Device Configuration NVL Register Map

Register Address

0x00

0x01

0x02

0x03

7

6

5

4

PRT3RDM[1:0]

PRT2RDM[1:0]

PRT12RDM[1:0]

PRT6RDM[1:0]

XRESMEN DBGEN

DIG_PHS_DLY[3:0]

3

2

1

0

PRT1RDM[1:0]

PRT0RDM[1:0]

PRT5RDM[1:0]

PRT4RDM[1:0]

PRT15RDM[1:0]

ECCEN

DPS[1:0]

CFGSPEED

The details for individual fields and their factory default settings are shown in Table 5-3:.

Table 5-3. Fields and Factory Default Settings

Field

PRTxRDM[1:0]

XRESMEN

DBGEN

CFGSPEED

DPS[1:0]

ECCEN

DIG_PHS_DLY[3:0]

Description

Settings

Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog

See “Reset Configuration” on page 38. All pins of the port 01b - high impedance digital

are set to the same mode.

10b - resistive pull up

11b - resistive pull down

Controls whether pin P1[2] is used as a GPIO or as an 0 (default) - GPIO

external reset. P1[2] is generally used as a GPIO, and not 1 - external reset

as an external reset.

Debug Enable allows access to the debug system, for 0 - access disabled

third-party programmers.

1 (default) - access enabled

Controls the speed of the IMO-based clock during the

device boot process, for faster boot or low-power

operation.

0 (default) - 12-MHz IMO

1 - 48-MHz IMO

Controls the usage of various P1 pins as a debug port.

See “Programming, Debug Interfaces, Resources” on

page 55.

00b - 5-wire JTAG

01b (default) - 4-wire JTAG

10b - SWD

11b - debug ports disabled

Controls whether ECC flash is used for ECC or for general 0 - ECC disabled

configuration and data storage. See “Flash Program

1 (default) - ECC enabled

Memory” on page 19.

Selects the digital clock phase delay.

See the TRM for details.

Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase/write cycles is limited

– see “Nonvolatile Latches (NVL)” on page 94.

Document Number: 001-84933 Rev. *L

Page 20 of 114

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