IDT70V659S 查看數據表（PDF） - Unspecified

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IDT70V659S

HIGH-SPEED 3.3V 128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

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IDT70V659S

High-Speed 3.3V 128K x 36 Asynchronous Dual-Port Static RAM

Waveform of Read Cycles(5)

tRC

ADDR

CE(6)

tAA (4)

tACE (4)

tAOE (4)

OE

BEn

tABE (4)

Preliminary

Industrial and Commercial Temperature Ranges

R/W

DATAOUT

BUSYOUT

tLZ (1)

(4)

VALID DATA

tBDD (3,4)

tOH

tHZ (2)

4869 drw 06

NOTES:

1. Timing depends on which signal is asserted last, OE, CE or BEn.

2. Timing depends on which signal is de-asserted first CE, OE or BEn.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

ICC

50%

ISB

tPD

50%

.

4869 drw 07

11

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