IDT79RC4640™
Timing Characteristics—RV4640
Cycle
MasterClock
1
2
3
4
tMCkHigh
tMCkLow
tMCkP
SysAD,SysCmd Driven
SysADC
SysAD,SysCmd Received
SysADC
D
D
D
tDM
tDOH
tDZ
tDO
D
D
tDS
tDH
D
D
Control Signal CPU driven
ValidOut*
Release*
Control Signal CPU received
RdRdy*
WrRdy*
ExtRqst*
ValidIn*
NMI*
Int*(5:0)
tDO
tDS
tDOH
tDH
* = active low signal
Figure 5 System Clocks Data Setup, Output, and Hold timing
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December 5, 2008