IDT5V9885C 查看數據表（PDF） - Integrated Device Technology
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IDT5V9885C Datasheet PDF : 39 Pages
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IDT5V9885C
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
RAM (PROGRAMMING REGISTER) TABLES
BIT #
BIT #
Register
ADDR 7 6 5 4 3 2 1 0
7
Hex Value
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
INDUSTRIAL TEMPERATURE RANGE
DES CRIPTION
No registers exist
No registers exist.
0x04 0 0 0 0 0 0 0 0
00
0x05 1 1 1 1 1 1 1 1
FF
0x06 0 0 1 1 0 0 0 0
30
0x07 0 0 0 0 0 0 0 0
00
0x08 0 0 0 0 0 0 0 0
00
OD IV0_C ONF I G0
0x09 0 0 0 0 0 0 0 0
00
OD IV0_C ONF I G1
0x0A 0 0 0 0 0 0 0 0
00
OD IV0_C ONF I G2
Rese rved
MFC
MFC=Manual Frequency Control Mode ('0'=All PLL Control (Default), "1"=PLL0 Control Only );
GINEN0 to GINEN5=GINx Pins Enable Bits, ("1"=Enable (Default), "0"=No Connect (Internal State will be "Low"));
GINEN5 GINEN4 GINE N3
XD RV[ 1:0]
XTALC AP[ 7:0]
GI N EN2
GINEN1
GIN EN0
XMDFRCV==Mcarnyustaall FdrreivqeusetnrecnygCtho(n"0tr0o"l =Mo1d.4eV,('0"0'=1A" l=l P2L.3LVC, "o1n0tr"o=l3(D.2eVfapukl-tp),k"s1w"=inPgLtLy0piCcaol,n"tr1o1l"O=XnTlyA)L;_IN with external clock-default); When
"G1I1N"E, NXT0AtoLCGAINPE[7N:05]=GvaINluxe PminustEanlsaoblbeeBsitest,to("1"0""=.Enable (Default), "0"=No Connect (Internal State w ill be "Low "));
B its 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
IP0[ 2: 0]_C ONF IG0
IP0[ 2: 0]_C ONF IG1
IP0[ 2: 0]_C ONF IG2
RZ 0[ 3:0] _CON FI G0
RZ 0[ 3:0] _CON FI G1
RZ 0[ 3:0] _CON FI G2
XDRV=crystal drive strength ("00" = 1.4V, "01" = 2.3V, "10"= 3.2V pk-pk swing typical, "11"=XTAL_IN with external clock-
default); When "11", XTALCAP[7:0] value must also be set to "0".
Bits 7,6, 3, 2, 1, 0 are reserved and should be set to "0"
XTAL load cap = 3.5pF+ (0.125 x XTALCAP[7:0]) , 3.5pF to 35.4pF; Each XTAL pin to GND;
(For example, "00000001"=0.125pF, "00000010"=0.25pF, "00000100"=0.5pF); Default = "00000000";
0x0B 0 0 0 0 0 0 0 0
00
OD IV0_C ONF I G3
IP0[ 2: 0]_C ONF IG3
0x0C 0 0 0 0 0 0 0 0
00
CP0[ 3: 0]_C ONF IG0
RZ 0[ 3:0] _CON FI G3
CZ 0[ 3:0] _CON FI G0
P LL0 LOOP FILTER SETTING
ODIV0_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use wi
0x0D 0 0 0 0 0 0 0 0
00
CP0[ 3: 0]_C ONF IG1
CZ 0[ 3:0] _CON FI G1
0x0E 0 0 0 0 0 0 0 0
00
0x0F 0 0 0 0 0 0 0 0
00
CP0[ 3: 0]_C ONF IG2
CP0[ 3: 0]_C ONF IG3
CZ 0[ 3:0] _CON FI G2
CZ 0[ 3:0] _CON FI G3
PLL0 LOOP FILTER SETTING
0x10 0 0 0 0 0 0 0 0
00
D0 [7:0]_CONFIG0
0x11 0 0 0 0 0 0 0 0
00
0x12 0 0 0 0 0 0 0 0
00
D0 [7:0]_CONFIG1
D0 [7:0]_CONFIG2
P LL0 INPUT DIVIDER D0 SE TTING
0x13 0 0 0 0 0 0 0 0
00
D0 [7:0]_CONFIG3
0x14 0 0 0 0 0 0 0 0
00
N0 [7:0]_CONFIG0
0x15 0 0 0 0 0 0 0 0
00
N0 [7:0]_CONFIG1
0x16 0 0 0 0 0 0 0 0
00
0x17 0 0 0 0 0 0 0 0
00
0x18 0 0 0 0 0 0 0 0
00
0x19 0 0 0 0 0 0 0 0
00
N0 [7:0]_CONFIG2
N0 [7:0]_CONFIG3
A0[ 3:0] _CON FI G0
A0[ 3:0] _CON FI G1
N 0[11: 8]_C ONF I G0
N 0[11: 8]_C ONF I G1
P LL0 MULTIPLIER SETTING
CONFIG0 will be sele cted if GINx are disabled and operating in MFC mode.
N0[11:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A 0[3:0]_CONFIGx - Part of PLL0 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
S SC_OFFSET0[5:0] - Spread Spectrum Fractional Multiplier Offset Value. S ee Spread Spectrum S ettings in register address range
0x 60-0x67
Total Multiplier Value M0 = 2 * N0[11:0] + A0 + 1 + SS_OFFSET0 * 1/64
When A0[3:0] = 0 and spread spectrum disabled, M0= 2 * N0[11:0];
When A0[3:0] > 0 and spread spectrum disabled, M0 = 2 * N0[11:0] + A0 + 1;
(Note : A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
0x1A 0 0 0 0 0 0 0 0
00
0x1B 0 0 0 0 0 0 0 0
00
0x1C 0 0 0 0 0 0 0 0
00
0x1D 0 1 0 0 0 0 0 0
40
0x1E 0 0 0 0 0 0 0 0
00
A0[ 3:0] _CON FI G2
N 0[11: 8]_C ONF I G2
A0[ 3:0] _CON FI G3
N 0[11: 8]_C ONF I G3
SP
SH
OE6
OE5
OE4
OE3
OE 2
OE1
S P=Shutdown/OE Polarity for SHUTDOWN/OE signal pin, ("0"= Active High (Default), "1"= Active Low);
OE x=Output Di sable Functi on for OUTx, ("1"=OUTx disabled base d on OE pin (De fault for OUT2 -6, Disable mode is defined by OEMx
OKC
OS6
OS5
OS4
OS3
OS 2
bits), "0"= Outputs enabled and no association with OE pin (Default));
OS1
OS x=Output Power Suspend function for OUTx, ("1"=OUTx will be suspended on GIN3/SUSPEND pin (MFC="1"), "0"= Always Enabled
(Defa ult));
P LLSx=Determines which PLLx to suspend when GIN3 is programmed to be used as SUS PEND, It suspends all the outputs associated
with that PLL, ("1"= suspends based on SUSPEND pin, "0"= PLL enabled and no association with SUSP END pin (Default)); It over-rides
OS x bits;
PLLS2
PLLS1
PLLS0
S H=Determines the function of the SHUTDOWN/OE signal pin. ("1"=Global Shutdown; this over-ri des OEx and OSx bits, "0"=Ouput
E nable/Disable (Default))
OK C=clock OK count, "0"=8 cycles, "1"=1024 cycles (Default) of Input Clocks for Revertive Switchover Mode:
A ddress 0x1D, Bit 7; Address 0x1E, Bits [7:3] are reserved and should be set to "0"
32
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