HYB3117800BSJ(1996) 查看數據表（PDF） - Siemens AG

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HYB3117800BSJ
(Rev.:1996)

2M x 8-Bit Dynamic RAM

Siemens AG 

HYB 3117800BSJ-50/-60/-70

2M x 8-DRAM

I/O1 I/O2

I/O8

WE

. CAS

&

No. 2 Clock

Generator

Data in

Buffer

8

Data out

Buffer

OE

8

Column

10 Address

A0

Buffer(10)

A1

10

Column

Decoder

A2

A3

Refresh

A4

Controller

A5

Sense Amplifier 8

I/O Gating

A6

A7

Refresh

A8

Counter (11)

A9

11

A10

1024

x8

Row

11 Address

Buffers(11)

Row

Memory Array

11 Decoder 2048 2048x1024x8

RAS

No. 1 Clock

Generator

Block Diagram

Semiconductor Group

4

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