AS7C33256PFD16A-200TQI 查看數據表（PDF） - Alliance Semiconductor

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AS7C33256PFD16A-200TQI

3.3V 256K × 16/18 pipeline burst synchronous SRAM

Alliance Semiconductor 

Key to switching waveform

Rising input

Timing waveform of read cycle

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

tCH

tADSPS

tADSPH

tADSCS

tADSCH

tAS

tAH

A1

A2

tWS

tWH

tCSS

tCSH

®

Falling input

tCYC

tCL

AS7C33256PFD16A

AS7C33256PFD18A

Undefined/don’t care

LOAD NEW ADDRESS

A3

CE1

tADVS

tADVH

ADV

OE

DOUT

(pipelined mode) tOE

tLZOE

Q(A1)

tHZOE

tOH

Q(A2)

tCD

ADV INSERTS WAIT STATES

tHZC

Q(A2Ý01)

Q(A2Ý10)

Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

DOUT

Q(A1)

(flow-through mode)

Q(A2Ý01)

Q(A2Ý10)

Note: Ý = XOR when LBO= HIGH/No Connect; Ý = ADD when LBO = LOW.

BW[a:b] is don’t care.

Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

tHZC

3/8/02; v.1.6

Alliance Semiconductor

P. 7 of 11

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