
MC74HC366A
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 3.
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 4.
LOGIC DETAIL
TO OTHER
FIVE BUFFERS
INPUT A
OUTPUT ENABLE 1
OUTPUT ENABLE 2
ONE OF 6
BUFFERS
VCC
Y
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6