M5M4V16169DRT-7 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M5M4V16169DRT-7

16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

MITSUBISHI ELECTRIC  

MITSUBISHI LSIs

M5M4V16169DTP/RT-7,-8,-10,-15

16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

DRAM Write Transfer 1&Read (WB1->WB2->DRAM->RB) Latency set=1

Buffer Write (DIN->WB1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

K

tRC

CMd#

CS#

RAS#

CAS#

tRP

tRAS

tRCD

tRWL

DTD#

Ad0-2

Ad3-11

Row

Row

Ad0=High

Ad1-Ad2=Low

**Col

WB2

Old Data

New Data[WB1(0-7)]

WB1

RB1

RB2

DRAM

SRAM

DQ0-15

01

Old Data

Old Data

234

tCBF

tCBF

56 7 01 2 34

tCBF

New Data[WB1(0-7)]

Latency x tK

New Data[WB1(0-7)]

DPD DPD PCG DPD DPD DPD ACT DNOP DWT1R DNOP PCG DPD DPD DPD

DES BW BW BW BW BW BW BW BW BW BW BW BW BW

01234567012345

New Data on RB appears as to latency set count. See DRT timing chart.

SRAM operation can be freely performed. ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).

MITSUBISHI ELECTRIC

57

(REV 1.0) Jul. 1998

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