Section Number
Title
Page
15.1.1.3 Hardware Trigger ..........................................................................................268
15.1.1.4 Analog Pin Enables .......................................................................................268
15.1.1.5 Temperature Sensor ......................................................................................268
15.1.1.6 Low-Power Mode Operation ........................................................................269
15.1.2 Features .........................................................................................................................270
15.1.3 Block Diagram ..............................................................................................................270
15.2 External Signal Description ..........................................................................................................271
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
Analog Power (VDDAD) ................................................................................................272
Analog Ground (VSSAD) ..............................................................................................272
Voltage Reference High (VREFH) .................................................................................272
Voltage Reference Low (VREFL) ..................................................................................272
Analog Channel Inputs (ADx) ......................................................................................272
15.3 Register Definition ........................................................................................................................272
15.3.1 Status and Control Register 1 (ADCSC1) ....................................................................272
15.3.2 Status and Control Register 2 (ADCSC2) ....................................................................274
15.3.3 Data Result High Register (ADCRH) ..........................................................................275
15.3.4 Data Result Low Register (ADCRL) ............................................................................275
15.3.5 Compare Value High Register (ADCCVH) ..................................................................276
15.3.6 Compare Value Low Register (ADCCVL) ...................................................................276
15.3.7 Configuration Register (ADCCFG) ..............................................................................276
15.3.8 Pin Control 1 Register (APCTL1) ................................................................................278
15.3.9 Pin Control 2 Register (APCTL2) ................................................................................279
15.3.10 Pin Control 3 Register (APCTL3) ................................................................................280
15.4 Functional Description ..................................................................................................................281
15.4.1 Clock Select and Divide Control ..................................................................................281
15.4.2 Input Select and Pin Control .........................................................................................282
15.4.3 Hardware Trigger ..........................................................................................................282
15.4.4 Conversion Control .......................................................................................................282
15.4.4.1 Initiating Conversions ...................................................................................282
15.4.4.2 Completing Conversions ...............................................................................283
15.4.4.3 Aborting Conversions ...................................................................................283
15.4.4.4 Power Control ...............................................................................................283
15.4.4.5 Sample Time and Total Conversion Time .....................................................283
15.4.5 Automatic Compare Function ......................................................................................285
15.4.6 MCU Wait Mode Operation .........................................................................................285
15.4.7 MCU Stop3 Mode Operation .......................................................................................285
15.4.7.1 Stop3 Mode With ADACK Disabled ............................................................285
15.4.7.2 Stop3 Mode With ADACK Enabled .............................................................286
15.4.8 MCU Stop1 and Stop2 Mode Operation ......................................................................286
15.5 Initialization Information ..............................................................................................................286
15.5.1 ADC Module Initialization Example ...........................................................................286
15.5.1.1 Initialization Sequence ..................................................................................286
15.5.1.2 Pseudo — Code Example .............................................................................287
15.6 Application Information ................................................................................................................288
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
18
Freescale Semiconductor
PRELIMINARY