CY7C9689A(2002) 查看數據表（PDF） - Cypress Semiconductor

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CY7C9689A
(Rev.:2002)

TAXI™-compatible HOTLink® Transceiver

Cypress Semiconductor 

CY7C9689A

Pin Descriptions (continued)

Pin

Name

I/O Characteristics

Signal Description

74 RANGESEL Static control input Range Select.

TTL levels

Selects the proper prescaler for the REFCLK input. If RANGESEL is LOW, the

Normally wired HIGH REFCLK input is passed directly to the Transmit PLL clock multiplier. If

or LOW

RANGESEL is HIGH, REFLCK is divided by two before being sent to the

Transmit PLL multiplier.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), with RANGESEL

HIGH or SPDSEL LOW, TXFULL toggles at half the REFCLK rate to provide a

character rate indication, and to show when data can be accepted.

51 RESET

Asynchronous

TTL input

Master Reset for Internal Logic.

Pulsed LOW for one or more REFCLK cycles.

28 FIFOBYP

Static control input

TTL levels

Normally wired HIGH

or LOW

FIFO Bypass Enable.

When asserted, the Transmit and Receive FIFOs are bypassed. In this mode

TXCLK is not used. Instead all transmit data must be synchronous to REFCLK.

Transmit FIFO status flags are synchronized to REFCLK. All received data is

synchronous to RXCLK output. Receive FIFO status flags are synchronized to

RXCLK (the recovered Receive PLL character clock).

When not asserted, the Transmit and Receive FIFOs are enabled. In this mode

all Transmit FIFO writes are synchronized to TXCLK, and all Receive FIFO

reads are synchronous to the RXCLK input.

50

BYTE8/10

Static control input 8/10-bit Parallel Data Size Select.

TTL levels

When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is enabled

Normally wired HIGH (ENCBYP is HIGH), 8-bit DATA characters and 4-bit COMMAND characters are

or LOW

captured at the TXDATA[7:0] or TXCMD[3:0] inputs (selected by the TXSC/D

input) and passed to the Transmit FIFO (if enabled) and encoder. Received

characters are decoded, passed through the Receive FIFO (if enabled) and

presented at either the RXDATA[7:0] or RXCMD[3:0] outputs and indicated by

the RXSC/D output.

When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is bypassed

(ENCBYP is LOW), the internal data paths are set for 10-bit characters. Each

received character is presented to the Receive FIFO (if enabled) and is passed

to the RXDATA[9:0] outputs.

When set for 10-bit data (BYTE8/10 is LOW) and the encoder is enabled

(ENCBYP is HIGH), 10-bit DATA characters and 2-bit COMMAND characters

are captured at the TXDATA[9:0] or TXCMD[1:0] inputs (selected by the

TXSC/D input) and passed to the Transmit FIFO (if enabled) and encoder.

Received characters are decoded, passed through the Receive FIFO (if

enabled) and presented at either the RXDATA[9:0] or RXCMD[1:0] outputs and

indicated by the RXSC/D output.

When set for 10-bit data (BYTE8/10 is LOW) and the encoder is bypassed

(ENCBYP is LOW), the internal clock data paths are set for 12-bit characters.

Each received character is presented to the Receive FIFO (if enabled) and is

passed to the RXDATA[9:0] and the RXCMD[1:0] outputs.

49 EXTFIFO

Static control input

TTL levels

Normally wired HIGH

or LOW

External FIFO Mode.

EXTFIFO modifies the active state of the RXEN and TXEN inputs and the timing

of the Transmitter and Receiver data buses. When configured for external

FIFOs (EXTFIFO is HIGH), TXEN is assumed to be driven by the empty flag of

an attached CY7C42X5 FIFO, and RXEN is assumed to be driven by the almost

full flag of an attached CY7C42X5 FIFO. In this mode the active data transition

is in the clock following the clock edge that “enables” the data bus.

When not configured for external FIFOs (EXTFIFO is LOW), TXEN is assumed

to be driven as a pipeline register and RXEN is assumed to be driven by a

controller for a pipeline register. In this mode the active data transition is within

the same clock as the clock edge that “enables” the data bus.

EXTFIFO also modifies the output state of the Receive and Transmit FIFO flags.

When configured for external FIFOs (EXTFIFO is HIGH), the Full and Empty

FIFO flags are active HIGH (the Half full flag is always active LOW). When not

configured for external FIFOs (EXTFIFO is LOW), all of the FIFO flags are active

LOW.

Document #: 38-02020 Rev. *C

Page 10 of 46

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