CY7C1442AV33(2005) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1442AV33
(Rev.:2005)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read/Write Cycle Timing[27, 29, 30]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

PRELIMINARY

ADSC

ADDRESS

A1

tAS tAH

A2

BWE,

BWX

tCES tCEH

CE

A3

A4

tWES tWEH

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

A5

A6

ADV

OE

Data In (D)

Data Out (Q)

tCO

tDS tDH

High-Z

High-Z

tCLZ

tOEHZ

Q(A1)

Q(A2)

Back-to-Back READs

D(A3)

Single WRITE

tOELZ

Q(A4)

Q(A4+1)

Q(A4+2)

BURST READ

Q(A4+3)

DON’T CARE

UNDEFINED

Notes:

29. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.

30. GW is HIGH.

D(A5)

D(A6)

Back-to-Back

WRITEs

Document #: 38-05383 Rev. *B

Page 23 of 27

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