CY7C1442AV33(2005) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1442AV33
(Rev.:2005)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle Timing[27, 28]

tCYC

PRELIMINARY

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

CLK

ADSP

ADSC

ADDRESS

BWE,

BWX

GW

CE

tCH tCL

tADS tADH

tADS tADH

tAS tAH

A1

A2

Byte write signals are

ignored for first cycle when

ADSP initiates burst

tCES tCEH

ADV

OE

Data In (D)

Data Out (Q)

High-Z

tDS tDH

t

OEHZ

D(A1)

BURST READ

Single WRITE

D(A2)

tWES tWEH

ADSC extends burst

tADS tADH

A3

tWES tWEH

ADV suspends burst

t

ADVS

tADVH

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note:

28. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Document #: 38-05383 Rev. *B

Page 22 of 27

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