AD7175-8 查看數據表（PDF） - Analog Devices

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AD7175-8

24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers

Analog Devices 

Data Sheet

Timing Diagrams

CS (I)

DOUT/RDY (O)

SCLK (I)

t1

t2

MSB

t3

t6

t5

LSB

t7

t4

I = INPUT, O = OUTPUT

Figure 2. Read Cycle Timing Diagram

CS (I)

t8

t11

SCLK (I)

DIN (I)

t9

t10

MSB

LSB

I = INPUT, O = OUTPUT

Figure 3. Write Cycle Timing Diagram

AD7175-8

Rev. 0 | Page 7 of 64

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