ISL6413IR 查看數據表（PDF） - Renesas Electronics

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ISL6413IR

Triple Output Regulator with Single Synchronous Buck and Dual LDO

Renesas Electronics 

ISL6413

Pin Descriptions

PVCC - Positive supply for the power (internal FET) stage of

the PWM section.

SGND - Analog ground for the PWM. All internal control

circuits are referenced to this pin.

EN _PWM- The PWM controller is enabled when this pin is

HIGH, and held off when the pin is pulled LOW. It is a CMOS

logic-level input (referenced to VIN).

VIN_LDO - This is the input voltage pin for LDO1 and LDO2.

EN_LDO - LDO1 and LDO2 are enabled when this pin is

HIGH, and held off when the pin is pulled LOW. It is a CMOS

logic-level input (referenced to VIN).

CT - Timing capacitor connection to set the 25ms minimum

pulse width for the RESET/RESET signal.

RESET, RESET - These complementary pins are the outputs

of the reset supervisory circuit, which monitors VIN. The IC

asserts these RESET and RESET signals whenever the

supply voltage drops below a preset threshold; keeping them

asserted for at least 25ms after VCC (VIN) has risen above the

reset threshold. These outputs are push-pull. RESET is LOW

when re-setting the microprocessor. The device will continue to

operate until VIN drops below the UVLO threshold.

PG_LDO - This is a high impedance open drain output that

provides the status of both LDOs. When either of the outputs

are out of regulation, PG_LDO goes LOW.

CC1 - This is the compensation capacitor connection for

LDO1. Connect a 0.033µF capacitor from CC1 to GND_LDO.

CC2 - This is the compensation capacitor connection for

LDO2. Connect a 0.033µF capacitor from CC2 to GND_LDO.

VOUT2 - This pin is the output of LDO2. Bypass with a 2.2µF,

low ESR capacitor to GND_LDO for stable operation.

GND_LDO - Ground pin for LDO1 and LDO2.

VOUT1 - This pin is the output of LDO1. Bypass with a 2.2µF,

low ESR capacitor to GND_LDO for stable operation.

PGND - Power ground for the PWM controller stage.

VOUT - This I/O pin senses the output voltage of the PWM

converter stage. For fixed 1.8V operation, connect this pin

directly to the output voltage.

PG_PWM - This pin is an active pull-up/pull-down able to

source/sink 1mA (min.) at 0.4V from VIN/SGND. This output is

HIGH when VOUT is within ±8% (typ.).

PG_PWM - This pin provides an inverted PG_PWM output.

LX - The LX pin is the switching node of synchronous buck

converter, connected internally at the junction point of the

upper MOSFET source and lower MOSFET drain. Connect

this pin to the output inductor.

VIN - This pin is the power supply for the PWM controller stage

and must be closely decoupled to ground.

SYNC - This is the external clock synchronization input. The

device can be synchronized to 500kHz to 1MHz switching

frequency.

GND - Tie this pin to the ground plane with a low impedance,

shortest possible path.

Functional Description

The ISL6413 is a 3-in-1 multi-output regulator designed for

wireless chipset power applications. The device integrates a

single synchronous buck regulator with dual LDOs. It supplies

three fixed output voltages 1.8V, 2.84V and 2.84V. The 1.8V is

generated using a synchronous buck regulator with greater

then 92% efficiency. Both 2.84V supplies are generated from

ultra low noise LDO Regulators. Under voltage lock-out

(UVLO) prevents the converter from turning on when the input

voltage is less then typically 2.6V

Additional blocks include an output over-current protections,

thermal sensor, PGOOD detectors, RESET function and

shutdown logic.

Synchronous Buck Regulator

The Synchronous buck regulator with integrated N- and

P-channel power MOSFET provides pre-set 1.8V for

BBP/MAC core supply. Synchronous rectification with internal

MOSFETs is used to achieve higher efficiency and reduced

number of external components. Operating frequency is

typically 750kHz allowing the use of smaller inductor and

capacitor values. The device can be synchronized to an

external clock signal in the range of 500kHz to 1MHz. The

PG_PWM output indicates loss of regulation on PWM output.

The PWM architecture uses a peak current mode control

scheme with internal slope compensation. At the beginning of

each clock cycle, the high side P-channel MOSFET is turned

on. The current in the inductor ramps up and is sensed via an

internal circuit. The error amplifier sets the threshold for the

PWM comparator. The high side switch is turned off when the

sensed inductor current reaches this threshold. After a

minimum dead time preventing shoot through current, the low

side N-channel MOSFET will be turned on and the current

ramps down again. As the clock cycle is completed, the low

side switch will be turned off and the next clock cycle starts.

The control loop is internally compensated reducing the

amount of external components. The PWM section includes an

anti-ringing switch to reduce noise at light loads.

The switch current is internally sensed and the minimum

current limit is 600mA.

Synchronization

The typical operating frequency for the converter is 750kHz if

no clock signal is applied to SYNC pin. It is possible to

synchronize the converter to an external clock within a

FN9129 Rev 0.00

Oct 29, 2003

Page 8 of 13

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