PEB2047-N 查看數據表（PDF） - Infineon Technologies

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PEB2047-N

Memory Time Switch Large

Infineon Technologies 

PEB 2047

PEB 2047-16

2.1 MTSL Internal Timing and Channel Delay

Figure 7 shows the chip internal timing of writing and reading the data memory for all possible

operation modes.

Control Memory Reset

Initialization of the device after a hardware reset (RES) is easily done with a µP-command “control

memory reset”. After finishing this procedure all control memory channels contain the information

“tristated”.

Evaluate Frame Measurement Signal

A command and an address (0 … 7) will be given by the µP. The rising edge of the corresponding

frame measurement signal (FS0 … FS7) will be evaluated. The exact timing of the FS edge can

then be read from an internal 12-bit register (resolution of a complete 8-kHz frame in half 16-MHz

clock periods).

MTSL-Selftest

The switching path of the MTSL including input buffer, data memory, control memory, output buffer

and timing control can be tested in the system by a built-in selftest. The two data memories DM0

and DM1 require two test procedures. Activating this mechanism takes (2 × 2.5) ms (4096 kHz),

(2 × 1.25) ms (8192 kHz) or (2 × 0.625) ms (16 384 kHz). Finally the result “selftest ok/selftest not

ok” can be read from the internal status register.

After test completion the control-memory is also reset.

2.2 Special Functions

The activity of all special functions can be read in the status register. Completion of these functions

is indicated by interrupts.

Semiconductor Group

15

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