IDT72V3622L15PFG8 查看數據表（PDF） - Integrated Device Technology

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IDT72V3622L15PFG8

3.3 VOLT CMOS SyncBiFIFO™ 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING TEMPERATURE

Commercial: VCC=3.3V± 0.30V; for 10ns (100 MHz) operation, VCC=3.3V ±0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant

Symbol

Parameter

IDT72V3622L10(1) IDT72V3622L15

IDT72V3632L10(1) IDT72V3632L15

IDT72V3642L10(1) IDT72V3642L15

Min. Max. Min. Max. Unit

fS

Clock Frequency, CLKA or CLKB

—

100

—

66.7 MHz

tCLK

Clock Cycle Time, CLKA or CLKB

10

—

15

—

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

4.5

—

6

—

ns

tCLKL

Pulse Duration, CLKA and CLKB LOW

4.5

—

6

—

ns

tDS

Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑

3

—

4

—

ns

tENS1

Setup Time CSA before CLKA↑; CSB before CLKB↑

4

—

4.5

—

ns

tENS2

Setup Time ENA, W/RA and MBA before CLKA↑; ENB, W/RB and MBB

before CLKB↑

3

—

4.5

—

ns

tRSTS

Setup Time, RST1 or RST2 LOW before CLKA↑ or CLKB↑(2)

5

—

5

—

ns

tFSS

Setup Time, FS0 and FS1 before RST1 and RST2 HIGH

7.5

—

7.5

—

ns

tFWS

Setup Time, FWFT before CLKA↑

0

—

0

—

ns

tDH

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

0.5

—

1

—

ns

tENH

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and

MBB after CLKB↑

0.5

—

1

—

ns

tRSTH

Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑(2)

4

—

4

—

ns

tFSH

Hold Time, FS0 and FS1 after RST1 and RST2 HIGH

2

—

2

—

ns

tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA,

and FFB/IRB

7.5

—

7.5

—

ns

tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB

12

—

12

—

ns

NOTES:

1. For 10ns speed grade only: VCC = 3.3V +/- 0.15V, TA = 0° to +70°C; JEDEC JESD8-A compliant.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.

5. Industrial temperature range is available by special order.

8

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