IRFR220, IRFU220, SiHFR220, SiHFU220
D.U.T
+
-
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-
-
+
RG
• dV/dt controlled by RG
+
• ISD controlled by duty factor "D"
• D.U.T. - device under test
- VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
Body diode forward
current
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode
Inductor current
Forward Drop
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level and 3 V drive devices
Fig. 14 - For N-Channel
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