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ICS85222AM-02

1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR

Integrated Device Technology 

ICS85222-02

1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, VDD

4.6V

Inputs, VI

Outputs, IO

Continuous Current

Surge Current

-0.5V to VDD + 0.5V

50mA

100mA

Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)

Storage Temperature, TSTG

-65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

VDD

Positive Supply Voltage

IDD

Power Supply Current

3.135

Typical

3.3

Maximum

3.465

50

Units

V

mA

TABLE 3B.

LVCMOS

/

LVTTL

DC

CHARACTERISTICS,

V

DD

=

3.3V±5%,

TA

=

0°C

TO

70°C

Symbol Parameter

Test Conditions

Minimum

V

Input High Voltage

2

IH

VIL

Input Low Voltage

-0.3

IIH

Input High Current CLK

VDD = VIN = 3.465V

IIL

Input Low Current CLK

VDD = 3.465, VIN = 0V

-5

Typical

Maximum

V + 0.3

DD

0.8

150

Units

V

V

µA

µA

TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

VOH

Output High Voltage; NOTE 1

VOL

Output Low Voltage; NOTE 1

VOX

Output Crossover Voltage

VSWING Peak-to-Peak Output Voltage Swing

NOTE 1: All outputs must be terminated with 50Ω to ground.

Minimum Typical Maximum Units

1.0

1.4

V

0

0.4

V

0.68

0.9

V

0.6

1.0

1.4

V

TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

fMAX

tPD

tsk(o)

Output Frequency

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 3

350

MHz

0.85

1.05

1.25

ns

25

ps

tsk(pp) Part-to-Part Skew; NOTE 4

250

ps

tR / tF

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

250

f ≤ 250MHz

45

f > 250MHz

40

500

ps

55

%

60

%

All outputs must be terminated with 50Ω to ground.

NOTE 1: Measured from V /2 of the input to the differential output crossing point.

DD

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load

conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR

3

ICS85222AM-02 REV. B SEPTEMBER 12, 2007

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